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19-1446; Rev 0; 3/99
+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
General Description
The MAX5122/MAX5123 low-power, 12-bit, voltage-output, digital-to-analog converters (DACs) feature an internal precision bandgap reference and output amplifier. The MAX5122 operates on a single +5V supply with an internal +2.5V reference, and offers a configurable output amplifier. If necessary, the user can override the on-chip, <10ppm/C voltage reference with an external reference. The MAX5123 has the same features as the MAX5122 but operates from a single +3V supply and has an internal +1.25V precision reference. The user-accessible inverting input and output of the amplifier allows specific gain configurations, remote sensing, and high output drive capability for a wide range of force/sense applications. Both devices draw only 500A of supply current, which reduces to 3A in power-down mode. In addition, their power-up reset feature allows for a user-selectable initial output state of either 0V or midscale and reduces output glitches during power-up. The serial interface is compatible with SPITM, QSPITM, and MICROWIRETM, which makes the MAX5122/MAX5123 suitable for cascading multiple devices. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit shift register loads data into the input register. The DAC register may be updated independently or simultaneously with the input register. Both devices are available in a 16-pin QSOP package and are specified for the extended-industrial (-40C to +85C) operating temperature range. For pin-compatible 14-bit upgrades, see the MAX5171/MAX5173 data sheet; for the pin-compatible 13-bit version, see the MAX5132/ MAX5133 data sheet. o Single-Supply Operation +5V (MAX5122) +3V (MAX5123) o Built-In 10ppm/C max Precision Bandgap Reference +2.5V (MAX5122) +1.25V (MAX5123) o SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface o Pin-Programmable Shutdown Mode and PowerUp Reset (0 or Midscale Output Voltage) o Buffered Output Capable of Driving 5k 100pF or 4-20mA Loads o Space-Saving 16-Pin QSOP Package o Pin-Compatible 13-Bit Upgrades Available (MAX5132/MAX5133) o Pin-Compatible 14-Bit Upgrades Available (MAX5171/MAX5173)
Features
MAX5122/MAX5123
Ordering Information
PART MAX5122AEEE MAX5122BEEE MAX5123AEEE MAX5123BEEE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP 16 QSOP 16 QSOP INL (LSB) 0.5 1 1 2
Applications
Industrial Process Control Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control Microprocessor-Controlled Systems
TOP VIEW
FB 1 OUT 2 RSTVAL 3 PDL 4 CLR 5 CS 6 DIN 7 SCLK 8
Pin Configuration
16 VDD 15 REFADJ 14 REF
MAX5122 MAX5123
13 AGND 12 PD 11 UPO 10 DOUT 9 DGND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
QSOP 1
________________________________________________________________ Maxim Integrated Products
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) FB, OUT to AGND ......................................-0.3V to (VDD + 0.3V) REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) QSOP (derate 8.00mW/C above +70C) .....................667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5122 (+5V)
(VDD = +5V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier configured in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection Ratio REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V VIH VIL VHYS IIN CIN VIN = 0 or VDD -1 200 0.001 8 1 3 0.8 V V mV A pF REFADJ = VDD VREF TCVREF VOUT/IOUT TA = +25C MAX5122A MAX5122B 0 IOUT 100A (sourcing) 2.475 2.5 3 10 0.1 4 3.3 7 1 2.525 V ppm/C V/A mA A N INL DNL VOS GE TCVFS PSRR MAX5122A MAX5123B 4.5V VDD 5.5V MAX5122A MAX5123B 12 -0.5 -1 -1 -10 -3 -0.2 3 10 20 0.5 1 1 10 3 10 30 250 Bits LSB LSB mV mV ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
ELECTRICAL CHARACTERISTICS--MAX5122 (+5V) (continued)
(VDD = +5V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier configured in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 4) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER REQUIREMENTS Power-Supply Voltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown VDD IDD ISHDN 4.5 500 3 5.5 600 20 V A A CS = VDD, fSCLK = 100kHz, VSCLK = 5Vp-p -0.1 SR To 0.5LSB, VSTEP = 2.5V 0.6 20 0 to VDD 0 2 5 0.1 V/s s V A ms nV-sec SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5122/MAX5123
ELECTRICAL CHARACTERISTICS--MAX5123 (+3V)
(VDD = +3V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier connected in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection Ratio REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis VIH VIL VHYS 200 2.2 0.8 V V mV REFADJ = VDD VREF TCVREF VOUT/IOUT TA = +25C MAX5123A MAX5123B 0 IOUT 100A (sourcing) 1.237 1.25 3 10 0.1 4 3.3 7 1 1.263 V ppm/C V/A mA A N INL DNL VOS GE TCVFS PSRR MAX5123A MAX5123B 2.7V VDD 3.3V MAX5123A MAX5123B 12 -1 -2 -1 -10 -5 -0.2 3 10 20 1 2 1 10 5 10 30 250 Bits LSB LSB mV mV ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
ELECTRICAL CHARACTERISTICS--MAX5123 (+3V) (continued)
(VDD = +3V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier connected in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 4) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER REQUIREMENTS Power-Supply Voltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown VDD IDD ISHDN 2.7 500 3 3.6 600 20 V A A CS = VDD, fSCLK = 100kHz, VSCLK = 3Vp-p -0.1 SR To 0.5LSB, VSTEP = 1.25V 0.6 20 0 to VDD 0 2 5 0.1 V/s s V A ms nV-sec VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V SYMBOL IIN CIN CONDITIONS VIN = 0 or VDD MIN -1 TYP 0.001 8 MAX 1 UNITS A pF
TIMING CHARACTERISTICS--MAX5122 (+5V)
(VDD = +5V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier connected in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay Time CS Rise to SCLK Rise Hold Time CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 CONDITIONS MIN 100 40 40 40 0 40 0 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
4
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
TIMING CHARACTERISTICS--MAX5123 (+3V)
(VDD = +3V 10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, output amplifier connected in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay Time CS Rise to SCLK Rise Hold Time CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 75 150 CONDITIONS MIN 150 75 75 60 0 60 0 200 200 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MAX5122/MAX5123
Note 1: Accuracy is guaranteed by the following table: VDD (V) 5 3 Accuracy Guaranteed From Code: 16 33 To Code: 4095 4095
Note 2: Offset is measured at the code closest to 10mV. V Note 2: The temperature coefficient is determined by the "box" method, in which the maximum OUT over the temperature range is divided by and the typical reference voltage. T Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points. Note 5: RLOAD = and digital inputs are at either VDD or DGND.
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Typical Operating Characteristics
(VDD = +5V, RL = 5k, CL = 100pF, output amplifier in unity-gain configuration, TA = +25C, unless otherwise noted.)
MAX5122 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5122/23 toc01
MAX5122 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 2.490 0 1,000 2,000 3,000 4,000 5,000
MAX5122/23 toc02
MAX5122 REFERENCE VOLTAGE vs. TEMPERATURE
MAX5122/23 toc03
0.20 0.15 0.10 INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 0 1,000 2,000 3,000 4,000
0.20
2.510
REFERENCE VOLTAGE (V)
2.505
2.500
2.495
5,000
-60 -40
-20
0
20
40
60
80
100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (C)
MAX5122 SUPPLY CURRENT vs. TEMPERATURE
MAX5122/23 toc04
MAX5122 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5122/23 toc05
MAX5122 SHUTDOWN CURRENT vs. TEMPERATURE
1.75 SHUTDOWN CURRENT (A) 1.50 1.25 1.00 0.75 0.50 0.25
MAX5122/23 toc06
500 450 SUPPLY CURRENT (A) 400 350 300 250 200 -60 -40 -20 0 20 40 60 80 (CODE = 000 HEX) (CODE = AAA HEX)
500
2.00
450 SUPPLY CURRENT (A)
400
(CODE = AAA HEX)
350 (CODE = 000 HEX)
300
250 100 4.0 4.5 5.0 5.5 6.0 TEMPERATURE (C) SUPPLY VOLTAGE (V)
0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MAX5122 FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE
RL = 5k CL = 100pF
MAX5122/23 toc07
MAX5122 FULL-SCALE OUTPUT ERROR vs. RESISTIVE LOAD
0.25 FULL-SCALE OUTPUT ERROR (LSB)
MAX5122/23 toc08
MAX5122 DYNAMIC RESPONSE RISE TIME
MAX5122/23-09
2.510
CS 5V/div
FULL-SCALE OUTPUT (V)
2.505
-0.50 OUT 1V/div -1.25
2.500
2.495
2.490 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-2.00 0.1 1 RL (k) 10 100 2s/div
6
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, CL = 100pF, output amplifier in unity-gain configuration, TA = +25C, unless otherwise noted.)
MAX5122 DYNAMIC RESPONSE FALL TIME
MAX5122/23-10
MAX5122/MAX5123
MAX5122 DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5122/23-11
MAX5122 MAJOR CARRY TRANSITION
MAX5122/23-12
CS 5V/div
SCLK 2V/div
CS 2V/div
OUT 1V/div
OUT 1mV/div AC COUPLED
OUT 100mV/div AC COUPLED
2V/div
2s/div
5s/div
MAX5123 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5122/23 toc13
MAX5123 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5122/23 toc14
MAX5123 REFERENCE VOLTAGE vs. TEMPERATURE
MAX5122/23 toc15
0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 1,000 2,000 3,000 4,000 INL (LSB)
0.15 0.10 0.05 DNL (LSB) 0 -0.05 -0.10 -0.15 -0.20 -0.25
1.260
REFERENCE VOLTAGE (V)
1.255
1.250
1.245
1.240 0 1,000 2,000 3,000 4,000 5,000 -60 -40 -20 0 20 40 60 80 100 DIGITAL INPUT CODE TEMPERATURE (C)
5,000
DIGITAL INPUT CODE
MAX5123 SUPPLY CURRENT vs. TEMPERATURE
MAX5122/23 toc16
MAX5123 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5122/23 toc17
MAX5123 SHUTDOWN CURRENT vs. TEMPERATURE
MAX5122/23 toc18
400 (CODE = AAA HEX) SUPPLY CURRENT (A) 350
400 (CODE = AAA HEX) SUPPLY CURRENT (A) 350
0.5
SHUTDOWN CURRENT (A)
0.4
300 (CODE = 000 HEX) 250
300
(CODE = 000 HEX)
0.3
250
0.2
200 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
200 2.50 2.75 3.00 3.25 3.50 SUPPLY VOLTAGE (V)
0.1 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, CL = 100pF, output amplifier in unity-gain configuration, TA = +25C, unless otherwise noted.)
MAX5123 FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE
MAX5122/23 toc19
MAX5123 FULL-SCALE OUTPUT ERROR vs. RESISTIVE LOAD
MAX5122/23 toc20
MAX5123 DYNAMIC-RESPONSE RISE TIME
MAX5122/23-21
1.260
0 FULL-SCALE OUTPUT ERROR (LSB)
CS 2V/div
FULL-SCALE OUTPUT (V)
1.255
-1
1.250
-2
OUT 400mV/div
1.245
-3
1.240 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-4 0.01 0.1 1 RL (k) 10 100 1s/div
MAX5123 DYNAMIC-RESPONSE FALL TIME
MAX5122/23-22
MAX5123 DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5122/23-23
MAX5123 MAJOR CARRY TRANSITION
MAX5122/23-24
CS 2V/div
SCLK 2V/div
CS 2V/div
OUT 400mV/div
OUT 500V/div AC COUPLED
OUT 100mV/div AC COUPLED
1s/div
2s/div
5V/div
8
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
Pin Description
PIN 1 2 3 NAME FB OUT RSTVAL Amplifier Inverting Sense Input (Analog Input) Analog Output Voltage. High impedance if part is in shutdown. Reset Value Input (Digital Input). 1: Connect to VDD to select midscale as the output reset value. 0: Connect to DGND to select 0V as the output reset value. Power-Down Lockout (Digital Input). 1: Normal operation. 0: Disallows shutdown (device cannot be powered down). Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the DAC will cause it to exit a software shutdown state. Active-Low Chip-Select Input (Digital Input) Serial Data Input. Data is clocked in on the rising edge of SCLK. Serial Clock Input Digital Ground Serial Data Output User-Programmable Output (Digital Output) Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a maximum shutdown current of 20A. Analog Ground Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V (MAX5122) or +1.25V (MAX5123) nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an external reference. Positive Power Supply. Bypass with a 0.1F capacitor in parallel with a 4.7F capacitor to AGND. FUNCTION
MAX5122/MAX5123
4
PDL
5 6 7 8 9 10 11 12 13 14
CLR CS DIN SCLK DGND DOUT UPO PD AGND REF
15 16
REFADJ VDD
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
CS DIN SCLK VDD AGND DGND
PDL PD
SR CONTROL
16-BIT SHIFT REGISTER
DOUT LOGIC OUTPUT UPO
RSTVAL CLR 12
DECODE CONTROL
FB
MAX5122 MAX5123
INPUT REGISTER
DAC REGISTER
DAC
OUT
BANDGAP 1.25V REFERENCE
4k
2X (X1)
2.5V (1.25V) REFERENCE BUFFER
REFADJ ( ) ARE FOR MAX5123 ONLY.
REF
Figure 1. Simplified Functional Diagram
_______________Detailed Description
The MAX5122/MAX5123 12-bit, force/sense DACs are easily configured with a 3-wire serial interface. They include a 16-bit data-in/data-out shift register and have a double-buffered digital input consisting of an input register and a DAC register. In addition, these devices employ precision bandgap references, as well as an output amplifier with accessible feedback and output pins that can be used to set the gain externally (Figure 1) or for forcing and sensing applications. These DACs are designed with an inverted R-2R ladder network (Figure 2) that produces a weighted voltage proportional to the digital input code.
FB
R
R
R
OUT
2R
2R D0
2R D9
2R D10
2R D11
Internal Reference
Both devices use an on-board precision bandgap reference with a low temperature coefficient of only 10ppm/C (max) to generate an output voltage of +2.5V (MAX5122) or +1.25V (MAX5123). The REF pin can source up to 100A and may become unstable with capacitive loads exceeding 100pF. REFADJ can be used for minor adjustments to the reference voltage.
REF* AGND
NOTE: SHOWN FOR ALL 1s ON DAC.
*INTERNAL REFERENCE: +2.5V (MAX5122), +1.25V (MAX5123); OR EXTERNAL REFERENCE
Figure 2. Simplified Inverted R-2R DAC Structure
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
The circuit in Figure 3 achieves a nominal reference adjustment range of 1%. Connect a 33nF capacitor from REFADJ to AGND to establish low-noise DAC operation. Larger capacitor values may be used, but will result in increased start-up delay. The time constant () for the start-up delay is determined by the REFADJ input impedance of 4k and CREFADJ: = 4k * CREFADJ
Output Amplifier
The MAX5122/MAX5123's DAC output is internally buffered by a precision amplifier with a typical slew rate of 0.6V/s. Access to the output amplifier's inverting input (FB) provides the user greater flexibility with amplifier gain setting and signal conditioning (see Applications Information). The output amplifier typically settles to 0.5LSB from a full-scale transition within 20s when it is connected in unity gain and loaded with 5k 100pF. Loads less than 1k may result in degraded performance.
MAX5122/MAX5123
External Reference
An external reference may be applied to the REF pin. Disable the internal reference by pulling REFADJ to VDD. This allows an external reference signal (AC- or DC-based) to be fed into the REF pin. For proper operation, do not exceed the input voltage range limits of 0 to (VDD - 1.4V) for VREF. Determine the output voltage using the following equation (REFADJ = VDD): VOUT = VREF [(NB / 4096) G] where NB is the numeric value of the MAX5122/ MAX5123 input code (0 to 4095), VREF is the external reference voltage, and G is the gain of the output amplifier, set by an external resistor-divider. The REF pin has a minimum input resistance of 40k and is code-dependent.
Power-Down Mode
These devices feature software- and hardware-programmable (PD pin) shutdown modes that reduce the typical supply current to 3A. To enter software shutdown mode, program the control sequence for the DAC as shown in Table 1. In shutdown mode, the amplifier output becomes highimpedance and the serial interface remains active. Data in the input registers is saved, allowing the MAX5122/MAX5123 to recall the output state prior to entering shutdown when returning to normal operation. To exit shutdown mode, load both input and DAC registers simultaneously or update the DAC register from the input register. When returning from shutdown to normal operation, wait 2ms for the reference to settle. When using an external reference, the DAC requires only 20s for the output to stabilize.
+5V
+3V
90k 400k 100k 33nF REFADJ
MAX5122
15k 400k 100k 33nF REFADJ
MAX5123
Figure 3a. MAX5122 Reference Adjust Circuit
Figure 3b. MAX5123 Reference Adjust Circuit
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD C2 0 0 0 0 1 1 1 1 1 C1 0 0 1 1 0 0 1 1 1 C0 0 1 0 1 1 0 0 1 1 D11 ............... D0 XXXXXXXXXXXX 12-Bit DAC Data 12-Bit DAC Data XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX 1XXXXXXXXXXX 00XXXXXXXXXX S0* FUNCTION S0* 0 0 0 0 0 0 0 0 0 No operation. Load input register; DAC register unchanged. Simultaneously load input and DAC registers; exit shutdown. Update DAC register from input register; exit shutdown. Shutdown DAC (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1; DOUT clocked out on SCLK's rising edge. Mode 0; DOUT clocked out on SCLK's falling edge (default).
X = Don't care
* S0 is a sub-bit and always zero.
VDD
Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables shutdown when low. When in shutdown mode, a high-to-low transition on PDL will wake up the DAC with its output still set to the state prior to power-down. PDL can also be used to wake up the device asynchronously. Power-Down Input (PD) Pulling PD high places the MAX5122/MAX5123 in shutdown. Pulling PD low will not return the MAX5122/ MAX5123 to normal operation. A high-to-low transition on PDL or appropriate commands (Table 1) via the serial interface are required to exit power-down mode.
DIN MOSI
SS
MAX5122 MAX5123 SCLK
SCK
SPI/QSPI PORT (PIC16/PIC17)
CS
I/O
Serial-Interface Configuration (SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5122/MAX5123 3-wire serial interface is compatible with SPI, QSPI, PIC16/PIC17 (Figure 4) and MICROWIRE (Figure 5) interface standards. The 2byte-long serial input word contains three control bits, 12 data bits in MSB-first format, and one sub-bit, which is always zero (Table 2). The MAX5122/MAX5123's digital inputs are double buffered, which allows the user to: * Load the input register without updating the DAC register, * Update the DAC register with data from the input register, * Update the input and DAC registers concurrently.
( ) ARE FOR PIC16/PIC17 ONLY.
CPOL = 0, CPHA = 0 (CKE = 1, CKP = 0, SMP= 0 SSPM3 - SSPM0 = 0001)
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
SCLK
SK MICROWIRE PORT
MAX5122 MAX5123
DIN
SO
CS
I/O
Figure 5. MICROWIRE Interface Connections
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
The 16-bit input word may be sent in two 1-byte packets (SPI-, MICROWIRE-, and PIC16/PIC17-compatible), with CS low during this period. The control bits C2, C1, and C0 (table 1) determine: * The clock edge on which DOUT transitions, * The state of the user-programmable logic output, * The configuration of the device after shutdown. The general timing diagram in Figure 6 illustrates how data is acquired. CS must be low for the part to receive data. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. When CS transitions high, data is latched into the input and/or DAC registers, depending on the setting of the three control bits C2, C1, and C0. The maximum serial clock frequency guaranteed for proper operation is 10MHz for the MAX5122 and 6.6MHz for the MAX5123. Figure 7 depicts a more detailed timing diagram of the serial interface.
MAX5122/MAX5123
PIC16 with SSP Module and PIC17 Interface
The MAX5122/MAX5123 are compatible with a PIC16/PIC17 microcontroller (C), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 4 and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 3 and 4. In SPI mode, the PIC16/PIC17 Cs allow eight bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit writings (Figure 6) are necessary to feed the DAC with three control bits, 12 data bits, and one sub-bit. DIN data transitions on the serial clock's falling edge and is clocked into the DAC on SCLK's rising edge. The first eight bits of DIN contain the three control bits (C2, C1, C0) and the first five data bits (D11-D7). The second 8-bit data stream contains the remaining bits (D6-D0), and the sub-bit S0.
Table 2. Serial Data Format
MSB ............................................................................... LSB Control Bits C2, C1, C0 16 BITS OF SERIAL DATA MSB ..... Data Bits ..... LSB D11................................D0 S0 Sub-Bit
CS COMMAND EXECUTED 1 DIN C2 C1 C0 D11 D10 D9 D8 8 D7 D6 9 D5 D4 D3 D2 D1 D0 16 S0
SCLK
Figure 6. Serial-Interface Timing
tCSW CS tCS0 SCLK tCH tCP DIN tDS DOUT tDO1 tDO2 tDH tCL tCSS tCSH tCS1
Figure 7. Detailed Serial-Interface Timing
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Table 3. Detailed SSPCON Register Contents
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX5122/MAX5123 SETTINGS X X 1 0 0 0 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16 SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial Port Enable Bit. 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI as serialport pins. Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
X = Don't care
Table 4. Detailed SSPSTAT Register Contents
CONTROL BIT SMP CKE D/A P S R/W UA BF BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX5130/MAX5131 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care
Serial Data Output
The contents of the internal shift-register are output serially on DOUT which allows for daisy-chaining of multiple devices (see Applications Information) as well as data readback. The MAX5122/MAX5123 may be programmed to shift data out of DOUT on the serial clock's rising edge (Mode 1) or on the falling edge (Mode 0). The latter is the default during power-up and provides a lag of 16 clock cycles, maintaining SPI, QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In Mode 1, the output data lags DIN by 15.5 clock cycles. During power-down, DOUT retains its last digital state prior to shutdown.
14
User-Programmable Output (UPO)
The UPO feature allows an external device to be controlled through the serial-interface setup (Table 1) thereby reducing the number of microcontroller I/O ports required. During power-down, this output will retain the last digital state before shutdown. With CLR pulled low, UPO will reset to the default state after wake-up.
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
__________Applications Information
Definitions
Integral Nonlinearity (INL) Integral nonlinearity (Figure 8a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 8b) is the difference between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal to 1LSB, the DAC guarantees no missing codes and is monotonic.
MAX5122/MAX5123
Offset Error The offset error (Figure 8c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
7 3 ANALOG OUTPUT VALUE (LSB) 6 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP O11 (1/2 LSB ) ANALOG OUTPUT VALUE (LSB) ACTUAL DIAGRAM
2 IDEAL DIAGRAM 1 OFFSET ERROR (+1 1/4 LSB) IDEAL OFFSET POINT 000 001 010 011 DIGITAL INPUT CODE
ACTUAL OFFSET POINT
0
Figure 8a. Integral Nonlinearity
Figure 8c. Offset Error
6 ANALOG OUTPUT VALUE (LSB) 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB) ANALOG OUTPUT VALUE (LSB)
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4 LSB)
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
4 0 000 100 101 110 111 DIGITAL INPUT CODE
Figure 8b. Differential Nonlinearity
Figure 8d. Gain Error
15
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is noise generated on the DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself.
+5V/+3V REF VDD
MAX5122 MAX5123
DAC
50k FB 50k OUT
AGND
DGND
Unipolar Output
Figure 9 shows the MAX5122/MAX5123 setup for unipolar, Rail-to-Rail(R) operation with a closed- loop gain of 2V/V. With its internal reference of +2.5V, the MAX5122 provides a convenient unipolar output range of 0 to +4.99878V, while the MAX5123 offers an output range of 0 to +2.49939V with its on-board +1.25V reference. Table 5 lists example codes for unipolar output voltages.
NOTE: GAIN = +2V/V
Figure 9. Unipolar Output Circuit Using Internal (+1.25V/+2.5V) or External Reference. With external reference, pull REFADJ to VDD.
Bipolar Output
The MAX5122/MAX5123 can be configured for unitygain bipolar operation (FB = OUT) using the circuit shown in Figure 10. The output voltage VOUT is then given by the following equation: VOUT = VREF [{G (NB / 4096)} - 1] where NB is the numeric value of the DAC's binary input code, VREF is the voltage of the internal (or external) precision reference, and G is the overall gain. The application circuit in Figure 10 uses a low-cost op amp (MAX4162) external to the MAX5122/MAX5123. Together with the MAX5122/MAX5123 this circuit offers an overall gain of +2V/V. Table 6 lists example codes for bipolar output voltages.
REF
+5V/+3V
50k
50k
VDD
MAX5122 MAX5123
DAC
FB
V+
VOUT OUT DGND AGND VMAX4162
Reset (RSTVAL) and C Clear (CLR) Functions
The MAX5122/MAX5123 DACs feature a clear pin (CLR), which resets the output to a certain value, depending upon how RSTVAL is set. RSTVAL = DGND selects an output of 0, and RSTVAL = VDD selects a midscale output when CLR is pulled low. The CLR pin has a minimum input resistance of 40k in series with a diode to the supply voltage (VDD). If the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (V CLR - VDD - 0.5V) / 40k. Note: Clearing the DAC will also cause the part to exit a software shutdown (PD = 0).
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
16
Figure 10. Unity-Gain Bipolar Output Circuit Using Internal (+1.25V/+2.5V) or External Reference. With external reference, pull REFADJ to VDD.
Daisy-Chaining Devices
Any number of MAX5122/MAX5123s may be daisychained by simply connecting the serial data output pin (DOUT) of one device to the serial data input pin (DIN) of the following device in the chain (Figure 11). Another configuration (Figure 12) allows several MAX5122/MAX5123 DACs to share one common DIN signal line. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. However, more I/O lines are required in this configuration, because each IC needs a dedicated CS line.
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Table 5. Unipolar Code Table (Gain = +1.6384V/V)
DAC CONTENTS MSB LSB SUB-BIT S0 0 0 0 0 0 0 MAX5122 +4.99878V +2.50122V +2.5V +2.49878V +1.2207mV 0V ANALOG OUTPUT INTERNAL REFERENCE MAX5123 +2.49939V +1.25061V +1.25V +1.24939V +610.35V 0V EXTERNAL REFERENCE MAX5122/MAX5123 VREF (4095 / 4096) 2 VREF (2049 / 4096) 2 VREF (2048 / 4096) 2 VREF (2047 / 4096) 2 VREF (1 / 4096) 2 0
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Table 6. Bipolar Code Table (Figure 10)
DAC CONTENTS MSB LSB SUB-BIT S0 0 0 0 0 0 0 MAX5122 +2.49878V +1.2207mV 0V -1.2207mV -2.49878V -2.5V ANALOG OUTPUT INTERNAL REFERENCE MAX5123 +1.24939V +610.35V 0V -610.35V -1.24939V -1.25V EXTERNAL REFERENCE MAX5122/MAX5123 VREF [ {2 (4095 / 4096)} - 1] VREF [ {2 (2049 / 4096)} - 1] VREF [ {2 (2048 / 4096)} - 1] VREF [ {2 (2047 / 4096)} - 1] VREF [ {2 (1 / 4096)} - 1] -VREF
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
SCLK I
SCLK II
SCLK III
MAX5122 MAX5123
DIN CS DOUT DIN CS
MAX5122 MAX5123
DOUT DIN CS
MAX5122 MAX5123
DOUT
TO OTHER SERIAL DEVICES
Figure 11. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
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17
+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
Using an External Reference with AC Components
The MAX5122/MAX5123 have multiplying capabilities within the reference input voltage range specifications. Figure 13 shows a technique for applying a sinusoidal input to REF, where the AC signal is offset before being applied to the reference input. V DD ). Bypass the power supply (VDD) with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance.
Layout Considerations
Digital and AC signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Power-Supply and Bypassing Considerations
On power-up, the input and DAC registers are cleared to either zero (RSTVAL = DGND) or midscale (RSTVAL =
DIN SCLK CS1 CS2 CS3 CS I CS II CS III TO OTHER SERIAL DEVICES
MAX5122 MAX5123
SCLK DIN SCLK DIN
MAX5122 MAX5123
DIN
MAX5122 MAX5123
SCLK
Figure 12. Multiple Devices Share One Common Digital Input (DIN)
+5V/ +3V +5V/+3V 26k AC REFERENCE INPUT
___________________Chip Information
MAX495
TRANSISTOR COUNT: 3308 SUBSTRATE CONNECTED TO AGND
500mVp-p
10k REF VDD FB
DAC
OUT
MAX5122 MAX5123
AGND DGND
Figure 13. External Reference with AC Components
18 ______________________________________________________________________________________
+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference
Package Information
QSOP.EPS
MAX5122/MAX5123
______________________________________________________________________________________
19
+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/C Internal Reference MAX5122/MAX5123
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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